COMMENT ⊗   VALID 00005 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	Program to test out the DR11-C
C00006 00003	Various interrupt routines
C00008 00004	VT05 I/O routines
C00010 00005	Data & Constants
C00012 ENDMK
C⊗;
;Program to test out the DR11-C

.INSRT STUFF.PAL[11,ARG]

;DR11-C definitions

DRCSR  = 763770		;Control and Status register
DROBUF = 763772		;Output Buffer register
DRIBUF = 763774		;Input Buffer register

DRIVEC = 340		;Request A & B interrupt vectors

.=DRIVEC
DRINTA			;Req A interrupt handler
240			;Level 5
DRINTB			;Req B interrupt handler
240			;Level 5


.=1000

START:	RESET
	MOV #START,SP		;Set up the stack
	MOV #BEGMES,R1		;Tell world who we are
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR %PS			;Priority level 0
	MOV #DRINTA,DRIVEC	;Set up interrupt vectors
	MOV #DRINTB,DRIVEC+4
	MOV #140,DRCSR		;Enable interrupts
	MOV #RAMES,R1		;Ready to cause a Req A interrupt
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR ADONE
	BIS #1,DRCSR		;Set CSR0 = Req A
1$:	TST ADONE
	BEQ 1$			;Wait around until interrupt handled

	MOV #NOIMES,R1		;Ready to not cause another one
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR ADONE
	MOV #100,R4
	BIS #1,DRCSR		;Set CSR0 = Req A
2$:	TST ADONE
	BNE TB			;Was interrupt handled?
	SOB R4,2$		;Wait a little bit

TB:	MOV #RBMES,R1		;Ready to cause a Req B interrupt
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR BDONE
	BIS #2,DRCSR		;Set CSR1 = Req B
1$:	TST BDONE
	BEQ 1$			;Wait around until interrupt handled

	MOV #NOIMES,R1		;Ready to not cause another one
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR BDONE
	MOV #100,R4
	BIS #2,DRCSR		;Set CSR1 = Req B
2$:	TST BDONE
	BNE BOTH		;Was interrupt handled?
	SOB R4,2$		;Wait a little bit

BOTH:	MOV #BIMES,R1		;Ready to cause both
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR BDONE
	CLR ADONE
	MOV #100,R4
	BIC #3,DRCSR		;Get ready to interrupt both
	BIS #3,DRCSR		;Set CSR0 & CSR1 = Req A & B
1$:	MOV BDONE,R0
	ADD ADONE,R0
	CMP R0,#2
	BGE SEND		;Both interrupts handled?
	SOB R4,1$		;Wait a little bit more if need be

SEND:	MOV #SNDMES,R1		;Ready to send a message
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	MOV #OBUF,OPTR		;Set up things for sending a message
	MOV #10,OCNT
	MOV #IBUF,IPTR
	MOV #10,ICNT
	MOV #RCVR,DRIVEC	;Set up interrupt vctors
	MOV #SNDR,DRIVEC+4
	CLR MDONE
	BIC #3,DRCSR		;Clear old interrupts
	BIS #2,DRCSR		;Start up the send routine
1$:	TST MDONE
	BEQ 1$			;Wait for it to finish
	MOV #RCVMES,R1		;All done with it
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	BPT
	JMP START

;Various interrupt routines

DRINTA: CLR R0
1$:	DEC R0
	BNE 1$			;Kill some time
	MOV #AMES,R1		;Tell world who we are
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR R0
2$:	DEC R0
	BNE 2$			;Kill some more time
	INC ADONE
	RTI			;All done here

DRINTB: CLR R0
1$:	DEC R0
	BNE 1$			;Kill some time
	MOV #BMES,R1		;Tell world who we are
	JSR PC,OUTSTR
	MOV #CRLF,R1
	JSR PC,OUTSTR
	CLR R0
2$:	DEC R0
	BNE 2$			;Kill some more time
	INC BDONE
	RTI			;All done here


;Now let's get serious

SNDR:	BIC #3,DRCSR		;Turn off interrupts
	DEC OCNT		;Any more?
	BLT 1$			; no
	MOV @OPTR,DROBUF	;Get next word to send
	ADD #2,OPTR
	INC DRCSR		;Set CSR0 = Req A
1$:	RTI

RCVR:	BIC #3,DRCSR		;Turn off interrupts
	DEC ICNT		;Any more?
	BGT 1$			; yes
	INC MDONE		; no - indicate all done
	BR 2$
1$:	MOV DRIBUF,@IPTR	;Get next word
	ADD #2,IPTR
	BIS #2,DRCSR		;Ready for next - set CSR1 = Req B
2$:	RTI

;VT05 I/O routines

OUTSTR:	MOVB (R1)+,R0		;Get next char
	BEQ 1$			;If done - quit
	JSR PC,OUTCHR		;Print it
	BR OUTSTR
1$:	JSR PC,OUTCHR		;Print a couple nulls
	JSR PC,OUTCHR
;	JMP OUTCHR

OUTCHR:	TST OUTSW		;Who does it go to?
	BEQ 2$
1$:	TSTB KBOS		;VT05 ready?
	BPL 1$			;Loop til it is
	MOVB R0,KBOR		;Print the char
	RTS PC
2$:	TSTB OREG		;Console ready?
	BNE 2$			;Wait til it is
	MOVB R0,OREG		;Output char
	RTS PC

INCHR:	TST OUTSW		;Where does it come from?
	BEQ 1$
	TSTB KBIS		;Anything typed on VT05?
	BPL 2$			; No
	MOVB KBIR,R0		; Read the char
	RTS PC
1$:	TSTB IREG		;Anything from the 10?
	BEQ 2$			; No
	MOVB IREG,R0		; Fetch the char
	CLRB IREG
	RTS PC
2$:	CLR R0			;No input
	RTS PC

;Data & Constants

OBUF:	.WORD 1,2,3,4,5,6,7,10	;Message to send
	.BLKW 20
IBUF:	.BLKW 40		;Where we'll store the message

OPTR:	OBUF		;What to send next
OCNT:	10		;How much left to send
IPTR:	IBUF		;Where to store next word
ICNT:	10		;How much left to receive

ADONE: 	.WORD 0		;Set by DRINTA interrupt routine
BDONE: 	.WORD 0		;Set by DRINTB interrupt routine
MDONE: 	.WORD 0		;Set when message has been sent

BEGMES:	.ASCII /πDR11-C Test Program/
CRLF:	.BYTE 12,15,0
RAMES:	.ASCIZ /πReady to generate an A interrupt/
RBMES:	.ASCIZ /πReady to generate a B interrupt/
BIMES:	.ASCIZ /πReady to generate both A & B interrupts/
NOIMES:	.ASCIZ /π... but this shouldn't/
AMES:	.ASCIZ /π - Handling an A request - /
BMES:	.ASCIZ /π - Handling a B request - /
SNDMES:	.ASCIZ /πSending a little message . . . /
RCVMES: .ASCIZ /πAll done now./


.END START